_early-design-and-validation-of-an-ai-accelerators-system-level-performance-using-an-hls-design-methodology.jpg "Early Design and Validation of an AI Accelerator’s System Level Performance Using an HLS Design Methodology from rapid hls Video Screenshot Preview")
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⏲ Duration: 20 min 98 sec
✓ Published: 26-May-2021
✓ Published: 26-May-2021
Description:
Presented at DVCon U.S. 2021nnPresenter: Michael Fingeroff, Siemens EDAnnThis workshop shows how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It focuses on using the opensource MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop demonstrates how pre-HLS simulation using MatchLib
Presented at DVCon U.S. 2021nnPresenter: Michael Fingeroff, Siemens EDAnnThis workshop shows how an HLS design and verification flow built around Catapult, and the ecosystem around it, could dramatically speed up the design of the AI/ML hardware accelerators compared to a traditional RTL based flow. It focuses on using the opensource MatchLib SystemC library from NVIDIA to perform rapid modelling and synthesis of the ML accelerator. The workshop demonstrates how pre-HLS simulation using MatchLib
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